Technical Briefs
TB-0001:	Reduction of input capacitor RMS current with increased phase count PDF
TB-0002:	Using diode emulation to reduce output voltage overshoot during a transient load release PDF
TB-0003:	An introduction to timing analysis for CHiL 33MHz high speed design applications PDF
TB-0004:	Layout guidelines for CHiL Semiconductor controllers with 33MHz high speed bus communications PDF
TB-0005:	Compensation of CHiL digital PWM controllers - Setting the compensation PID parameters and low-pass filters (KPOLES) PDF

User Notes
UN-0001:	How to program the CHL8100 and CHL831X Family of controllers with a Load Line less than 0.6mOhms PDF
UN-0002:	Understanding the Register Map for the CHL8314/6/8 CHiL VR11.1 controllers PDF
UN-0003:	Understanding the Register Map for the CHL8266 CHiL graphics controller PDF
UN-0004:	Designing voltage regulator (VR) solutions for AMD G34 IDDspike requirements PDF
UN-0006:	Understanding the Register Map for the CHL8112A/B CPU controller PDF
UN-0008:	Understanding the Register Map for CHiL graphics controllers, CHL8203, CHL8212, CHL8213, and CHL8214 PDF
UN-0010:	Understanding the Register Map for CHiL graphics controllers, CHL8225G and CHL8228G PDF
UN-0011:	Understanding the Register Map for CHiL Intel VR12 controllers, CHL8325A/B, CHL8326, CHL8328 PDF
UN-00121:	Understanding the Register Map for CHiL Intel VR12 controllers, CHL8102, CHL8103, CHL8104, and CHL8113 PDF